# Residual Stress of Curvature Sapphire Substrate with GaN Film Released by the Application of Trench Structures

Ming-Han Liao^{1, *}, Jyh-Jone Lee^{1}, Chih-Hua Chen^{1}, Ssu-Chieh Kao^{1}, Kuan-Chou Chen^{2}, and Cho-Fan Hsieh^{2}

^{1} Department of Mechanical Engineering, National Taiwan University, Taiwan^{2} Industrial Technology Research Institute (ITRI), Taiwan

(Received 21 March 2013; Accepted 24 April 2013; Published on line 1 December 2013)

*Corresponding author: mhliaoa@ntu.edu.tw

DOI: 10.5875/ausmt.v3i4.202

Abstract: Serious wafer curvature and residual stress are formed during the growth of an epi-GaN layer on Sapphire substrates due to the different thermal expansion coefficients in these two materials. By using theoretical analysis and a simulation model using the finite element method to describe the realistic shape of wafer curvature on epi-GaN wafers, we examine the influence which different thickness and thermal expansion coefficients in the top epi-GaN layer have on wafer curvature reduction. In addition a new process to reduce wafer curvature and to relax residual stress is proposed. With an additional laser treatment on a sample surface after the growth of the top epi-GaN layer on a Sapphire substrate has taken place, the wafer curvature can be reduced to ~ 37 µm from the original ~ 45 µm in 2 inch wafers with an optimized surface structure design.

Keywords: Stress; GaN; LED; Laser; Surface Structure

## Introduction

Strain is extensively used in the current semiconductor industry [1-3] including solar cell devices [4] and light-emitting diodes (LEDs) [5] because it can change material properties such as energy band structure [6], carrier effective mass [6], and radiative recombination rates [5]. One of the key stressors in the current industry is called an Epi-layer stressor [7]. By mismatching the lattice constants and different coefficients of thermal expansion (CTE) between two different materials, high strain can be produced during the thermal manufacturing process. However, too much strain can result in damage to the devices and low yield for real production [8]. How to accurately control the strain level in a device and how to measure local strain has recently become an important topic [9, 10]. In the GaN/Sapphire system for the application of LEDs, Jang [11] and Krost [12] found that ~ 230 MPa stress and 30-60 µm wafer curvature developed in 2 inch wafers, which cannot be accepted for production. Jang [11] also found that this wafer curvature is non-uniform and hard to control due to the high wafer surface temperature required for the process. As the size of Sapphire wafer substrate and process temperature increased for higher throughput, the wafer curvature becomes an even more important issue due to the fact that wafer curvature increases with the larger size of the wafer and higher process temperature. Although patterning the Sapphire substrate [13, 14] can partially solve this issue, the quality of the top epi-GaN layer will be influenced when this epi-GaN layer is grown on a patterned substrate. In this work, we propose to use an additional laser treatment on the top or bottom of the sample after the growth of an epi-GaN layer on a Sapphire substrate which results in the drilling of a hole. It can provide extra space to reduce the residual stress and to reduce wafer curvature. Most importantly, it is shown that this proposed process will not influence the quality of the epi-GaN layer. The optimized surface structure with the laser treatment is also further investigated by means of a finite element simulation and theoretical analysis

## Experiment

The epi-GaN layer in this study is grown by applying metal organic chemical vapor phase epitaxy (MOVPE) on the c-axis oriented Sapphire in an AIXTRON 200/4 RF-S system with the gas foil rotation in 1–3 Hz.

Optical curvature measurement is performed using an adapted optical sensor together with an EpiCurve® TT system from a commercial LayTec EpiRAS 200 spectrometer [15] on the top window of the stainless steel housing of the MOVPE reactor. We use a nearly perpendicular incidence for wafer curvature measurement. The curvature system has been considerably improved yielding a much better signal-to-noise ratio. We use a focused He–Ne laser as the light source and a CMOS camera (1024 × 1024 pixels) which has advantages over a line camera because of the rotating sample as a detector. The two parallel light beams pass nearly perpendicular to the sample through a hole in the liner which is only 5 mm in diameter. The reflected beams become divergent or convergent upon reflection at the curved sample surface and fall on the camera where the distance between the two beams is measured as a pixel distance, which is proportional to wafer curvature. The high speed sensor allows 18–20 pictures to be taken per second.

In order to simulate the behavior of residual stress and wafer curvature in the GaN/Sapphire system with and without surface structure process treatment, the finite element method (FEM) is used by a proprietary version of the ANSYS. To comprehend stress relaxation from the surface structure, a displacement boundary condition equal to Burgers vector is introduced at the surface of the top epi-GaN layer and at the interface between the epi-GaN layer and the Sapphire substrate. We apply a bond-counting variant of the lattice kinetic Monte Carlo (LKMC) method [3, 16] in order to study stress relaxation in the drilling hole aggregation in the epi-GaN layer and Sapphire substrate. The development of a quantitatively accurate LKMC simulator, with a database generated by molecular dynamics simulations [16] for model regression and validation, is carried out. We find that lattice models such as LKMC, which by definition do not explicitly accommodate off-lattice degrees-of-freedom, are unable to properly describe aggregation dynamics unless special care is applied to include the effects of off-lattice relaxation, especially at elevated temperatures. A novel spatial coarse-graining approach, which is aimed at greatly extending the scope of the LKMC simulations, along with numerical closure rules, which allow for the consideration of strong interactions between particles, is generally presented and included in aggregating systems in our simulation model [3].

Some important parameters used in our simulations are listed in Table 1.

For relaxation of residual stress using the surface structure process, the commercial solution is to use the Pattern Sapphire Process (PSP). The detailed process conditions for the PSP used in this work can be referred to in [14]. In addition to the PSP structure, we also propose to use an additional fiber laser treatment with 500 mW on the sample after the epitaxy of the GaN layer in this work to result in a drilling hole on the top GaN surface layer (Type B) or on the bottom Sapphire substrate (Type A). This process can provide extra space for the relaxation of residual stress and for the reduction of wafer curvature. The laser treatments used in this work are characterized by high-power and short-duration pulsed-laser strikes at the surface to drill small holes. This process is shown to have reduced the heat affect zone.

## Results and Discussions

Figure 1 shows the simulation results for wafer curvature in 2 inch wafers with different boundary conditions and their corresponding experimental data. The wafer curvature which results is caused by the difference of CTE between the top epi-GaN layer and the bottom Sapphire substrate. Our simulation results match very well with the experimental data (~45 µm wafer curvature and ~231 MPa surface stress). It also can be found that the thickness and the CTE of the top epi-GaN layer influence the wafer curvature substantially.

As the size of the Sapphire wafer and the process temperature are increased in order to reduce cost and to increase throughput the simulation data in Figure 2 shows that wafer curvature becomes an even more important issue because the wafer curvature increases as the size of the wafer and the temperature of the process increase.

In order to solve the issue of wafer curvature, a PSP technology has recently become very popular in the InGaN/GaN-based LED industry. In this work, a PSP structure is studied first. The specifications of our PSP LED structure are shown in Figure 3, where “D” is the hole diameter, “P” is the pitch dimension between two holes, and “d” is the depth dimension of the holes. For the commercial PSP structure (D=1µm, P=2µm, and d=1.5µm), wafer curvature indeed can be reduced from the original ~ 45 µm to ~ 39 µm in 2 inch wafers. However, the production cost and the quality of the epi-GaN layer are increased and influenced [13], respectively.

Therefore, we propose to use an additional laser treatment which drills holes on the bottom Sapphire substrate (Type A structure shown in Figure 4) or on the top GaN layer (Type B structure shown in Figure 4). With this treatment relaxation of residual stress after epitaxy of the epi-GaN can be achieved. The structural dimensions of the PSP, Type A, and Type B structures shown in Figure 5 are kept the same (D=1 µm, P=2 µm, and d=1.5 µm) in order to produce a fair comparison. Based on our simulation results, shown in Figure 5, the Type B surface structure has a similar capability to reduce wafer curvature as the commercial PSP structure, even if the dimension of wafer size is increased (8 inch wafer). It is important to note that the Type B surface structure process used in this work will not influence the quality and epitaxy of the GaN layer, and can save on production cost because this additional laser treatment is used after the epitaxy of the top GaN layer on the Sapphire substrate has formed. The simulation results shown in Figure 5 also indicate that the top GaN surface structures in the PSP and Type B cases play a more important role for reduction of wafer curvature than the structures in the GaN/Sapphire interface for the PSP case and in the bottom Sapphire structure for the Type A case.

In order to further enlarge and optimize the benefit for wafer curvature reduction using the Type B structure, we investigate the different hole depth (d) (from 1 µm to 1.5 µm) effects for wafer curvature reduction as shown in Figure 6. It shows that wafer curvature can be reduced with increases in hole depth (d). In addition, the influence of different dimensions of pitch (P from 2 µm to 1.2 µm) and surface hole diameter (D from 1 µm to 0.1 µm) on wafer curvature are also simulated and given in Figure 7. It shows that pitch dimension is more sensitive to wafer curvature reduction than surface hole diameter. With the optimal dimension of the surface structure in the Type B case (D=1 µm, P=1.2 µm, and d=1.5 µm), 2 inch wafer curvature can be reduced to ~37µm from the original ~45 µm in the control wafer as compared with the ~ 39 µm in the commercial PSP structure (D=1 µm, P=2 µm, and d=1.5 µm).

## Conclusion

Due to the different thermal expansion coefficients between an epi-GaN layer and a Sapphire substrate, the residual stress and wafer curvature in light-emitting diodes become worse when the wafer size and process temperature are increased.

In this study we investigated wafer curvature sensitivity at different levels of thickness and with different expansion coefficients using the finite element method. As a result of this study we propose two different types of surface structures which can be created using additional laser treatments (Type B: top GaN surface structure and Type A: bottom Sapphire structure) designed to relax the residual stress in this work. While the commercial patterned Sapphire substrate process can also be used to relax residual stress, it influences the epi-quality of the GaN layer and increases the cost of production.

The proposed method in the Type B structure has a similar capability to reduce wafer curvature as the typical patterned Sapphire substrate process when applied to a structure with the same surface dimensions. It will not, however, influence the LED light emission quality and can save on production costs. Through the optimization of the surface structure in the proposed Type B case, the wafer curvature can be reduced to ~ 37 µm from the original ~ 45 µm in a 2 inch wafer.

## Acknowledgement

This work is supported by the National Science Council (NSC), Taiwan, under Grants Nos. 100-2221-E-002-253-, 101-2218-E-002-010-, and 101-2628-E-002-018-MY3, and the Ministry of Economic Affairs (MEA), Taiwan, under Grant No. 101-EC-17-A-01-S1-219. Project support from the Industrial Technology Research Institute is also appreciated.

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